A new type of CMOS compatible, NDR capable FET is disclosed in the following King et al. applications: Ser. No. 09/603,101 entitled “A CMOS-PROCESS COMPATIBLE, TUNABLE NDR (NEGATIVE DIFFERENTIAL RESISTANCE) DEVICE AND METHOD OF OPERATING SAME”; and Ser. No. 09/603,102 entitled “CHARGE TRAPPING DEVICE AND METHOD FOR IMPLEMENTING A TRANSISTOR HAVING A NEGATIVE DIFFERENTIAL RESISTANCE MODE”; and Ser. No. 09/602,658 entitled “CMOS COMPATIBLE PROCESS FOR MAKING A TUNABLE NEGATIVE DIFFERENTIAL RESISTANCE (NDR) DEVICE all of which were filed Jun. 22, 2000 and which are hereby incorporated by reference as if fully set forth herein. The advantages of such device are well set out in such materials, and are not repeated here.
In preferred embodiments, this device typically uses a dielectric layer for creating a charge trapping region that rapidly traps/detraps charge carriers. A number of different techniques are explained for forming said traps to achieve a desired NDR effect. It is apparent, nonetheless, that additional processing techniques (and/or more optimized versions of the processes described in King et al) would be beneficial for expanding the availability fo such devices.
A current trend also is to use so called silicon-on-insulator substrates to manufacture integrated circuits. It is expected that this technology will experience rapid growth in the years to come, but to date, only two terminal NDR diodes have been implemented in such environments. Thus, there is clearly a need for an NDR device that is as easy to integrate as a conventional FET in such technology.
Another growing trend is the use of NDR devices as load elements in SRAM memory cells and other circuit applications. To date, such NDR devices have been limited to two terminal, diode type structures which have operational limitations as well as integration complexities with CMOS processing. Furthermore, it is not possible, for example, to implement a low power memory cell using a single channel technology; current approaches are limited to conventional CMOS, where both p and n type transistors are required. Accordingly, there is an apparent compelling need for a low cost, easily integrable NDR solution for such applications as well.